I. Technical Field
This invention relates, in general, to the design and production of semiconducting microchips. More particularly, this invention relates to methods for establishing electrical contacts between components of a semiconducting microchip.
II. Background Art
The semiconductor microchip has become a ubiquitous part of everyday life. Microchips are obviously found in computers, but are also found in everything from garage door openers to cars to children's toys. The microchip has become a vital and important part of everyday life for virtually every person in the United States, and most people around the world.
Microchips are constructed from silicon or other semiconductors. By selectively introducing impurities into particular regions of the silicon and by selectively depositing and removing other materials onto the silicon, circuits may be constructed on a silicon chip. A chip is built using a process known as "photolithography". Photolithography consists of placing chemicals upon the surface of the chip and exposing that surface to radiation, typically light of a carefully selected wavelength, to selectively cause chemical reactions at particular locations on the chip's surface. Special compounds called "photoresists" or simply "resists" have been created for this purpose. Different resists have different chemical and physical properties and respond to different wavelengths of light. The location of the chemical reactions is controlled by "masking" the surface of a chip so that only certain portions of it receive radiation. The results of these chemical reactions allow certain parts of the surface of the chip to be removed or modified. By sequentially applying these processes a layer of electrically connected devices, such as transistors and capacitors can be formed.
A single layer of a chip may be electrically connected in a variety of ways. One method of electrically connecting a chip layer is to use the selective deposition and removal of a metal to create lines of metal on the surface of a chip to connect circuit components. According to this process, a thin metallic film, typically aluminum, is deposited over the surface of a chip. A layer of resist is then applied over the surface of the film. The resist is next exposed to light of an appropriate wavelength using a mask that exposes a pattern of relatively narrow lines on the resist. The resist is then developed and etched, leaving aluminum in the pattern exposed on the resist. This pattern of aluminum forms the electrical connections for that layer of the chip.
A newer method of electrically connecting one layer of a chip is known as the "damascene" process. According to the damascene process, a silicon dioxide layer is grown over the surface of a chip. A layer of resist is applied to the silicon dioxide layer. The resist is then exposed to establish the appropriate pattern of interconnections. The resist is then developed and an etch is performed. This etch produces trenches in the silicon dioxide patterned to form the interconnections for that layer. A metal, typically aluminum, copper or tungsten, is next deposited over the surface of the chip, filling the trenches. The metal is then planarized so that it is removed from the surface of the chip except where it filled in the trenches. As a result, metal fills the trenches to form a pattern of interconnections. Horizontal connections, are generally referred to as "wires". A typical chip includes one layer of devices and multiple layers of wiring connected to those devices.
While a microchip may consist of a single layer of wiring, as a practical matter several layers are required to obtain sufficient chip function in today's technologically advanced world. The layers of the microchip are typically separated by silicon dioxide or another dielectric to prevent one layer of a chip from interfering with the operation of another layer. However, these layers of a chip must be electrically connected at the appropriate locations through the silicon dioxide. Otherwise, each individual layer would exist in isolation from the other layers, and the chip could not perform properly.
To connect layers of a chip, the silicon dioxide that separates wiring layers must be penetrated and the components of the layers electrically connected in an appropriate manner. One common way to electrically connect the layers of a chip is the "dual damascene" method. This method is known as dual damascene because it is similar to the damascene process that was described above for use in creating wiring to electrically connect components on one layer of a chip. The first step is to create trenches in the silicon dioxide for wires as described above. The second step is to create openings through the silicon dioxide to the lower chip layer. The openings are made using a process of applying a resist, masking, exposing, developing, and etching, as was set forth above. The openings through a layer of silicon dioxide are commonly referred to as "vias". A via is typically formed using a square mask image which, due to diffraction effects, prints a circle on the photoresist. A square mask image, such as is used to print a via, is not suitable for most image enhancement techniques that are used in photolithography, as those techniques require elongated images to function most effectively. After developing the resist and etching the silicon dioxide, a conductor, typically aluminum, copper or tungsten, is deposited over the surface of the chip, thus filling the vias and the trenches. The conductor in the vias forms vertical structures referred to as "studs" or "interconnects" that extend through the silicon dioxide to electrically connect the components above the silicon dioxide to the components below the silicon dioxide. For an interconnect to function properly, it must make an adequate contact with the appropriate circuit element on each layer it is to connect. Typically, a via must be created through the silicon dioxide to extend between two trenches on adjacent layers.
The dual damascene method of electrically connecting layers of a microchip requires a careful alignment of vias and trenches. The tolerances that must be allowed to assure a proper alignment of vias and trenches limits the density that may be obtained on a microchip. The conventional method of fabricating vias and trenches is to first create the trenches and then create the vias, as separate steps in the fabrication process. Each step necessarily requires the substeps of applying resist, masking and exposing the surface, developing the resist, and then etching the surface.
The need exists for a new process to allow for improved alignment of vias and trenches so that space on a chip may be used more advantageously. An improved method should allow conventional image enhancement techniques to be applied to the printing of vias, while still creating a compact, non-elongated via on the chip. The need also exists for a new process requiring fewer processing steps in creating vias and trenches, to simplify chip fabrication and to reduce fabrication costs.